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| VS28F016SV MS28F016SV 16-Mbit (1-Mbit x 16 2-Mbit x 8) FlashFile TM MEMORY Y VS28F016SV b 40 C to a 125 C SE2 Grade MS28F016SV b 55 C to a 125 C QML Certified SE1 Grade SmartVoltage Technology User-Selectable 3 3V or 5V VCC User-Selectable 5V or 12V VPP Three Voltage Speed Options 80 ns Access Time 5 0V g5% 85 ns Access Time 5 0V g10% 120 ns Access Time 3 3V g10% 1 Million Erase Cycles per Block Typical 14 3 MB sec Burst Write Transfer Rate Y Y Y Configurable x8 or x16 Operation 56-Lead SSOP Plastic Package Backwards-Compatible with VE28F008 M28F008 and 28F016SA Command Set Revolutionary Architecture Multiple Command Execution Write During Erase Command Super-Set of the Intel VE28F008 M28F008 Page Buffer Write Multiple Power Savings Modes Two 256-Byte Page Buffers State-of-the-Art 0 6 mm ETOX TM IV Flash Technology Y Y Y Y Y Y Y Y Y Intel's VS MS28F016SV 16-Mbit FlashFiIe TM Memory is the latest member of Intel's high density high performance memory family for the Industrial Special Environment and Military markets Its user selectable VCC and VPP (SmartVoltage Technology) innovative capabilities 100% compatibility with the VE28F008 and M28F008 multiple power savings modes selective block locking and very fast read write performance make it the ideal choice for any applications that need a high density and a wide temperature range memory device The VS MS28F016SV is the ideal choice for designers who need to break free from the dependence on slow rotating media or battery backed up memory arrays With two product grades (SE1 b 55 C to a 125 C and SE2 b 40 C to a 125 C) available the VS MS28F016SV is perfect for the non-PC industries like Telecommunications Embedded Industrial Automotive Navigation Wireless Communication Commercial Aircraft and all Military programs The VS MS28F016SV's x8 x16 architecture allows for the optimization of the memory to processor interface The flexible block locking options enable bundling of executable application software in a Resident Flash Array (RFA) PCMCIA Memory or ATA Cards or Memory modules The VS MS28F016SV is offered in a 56-lead SS0P (Shrink Small Outline Package) and is manufactured on Intel's 0 6 mm ETOX TM IV process technology Other brands and names are the property of their respective owners Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata COPYRIGHT INTEL CORPORATION 1995 December 1995 Order Number 271312-002 VS28F016SV MS28F016SV FlashFile TM MEMORY CONTENTS 1 0 INTRODUCTION 1 1 Enhanced Features 1 2 Product Overview 2 0 DEVICE PINOUT 2 1 Lead Descriptions 3 0 MEMORY MAPS 3 1 Extended Status Registers Memory Map 4 0 BUS OPERATIONS COMMANDS AND STATUS REGISTER DEFINITIONS 4 1 Bus Operations for Word-Wide Mode (BYTE e VIH) 4 2 Bus Operations for Byte-Wide Mode (BYTE e VIL) 4 3 VE28F008 or M28F008 Compatible Mode Command Bus Definitions 4 4 VS MS28F016SV-Performance Enhancement Command Bus Definitions 4 5 Compatible Status Register 4 6 Global Status Register 4 7 Block Status Register 4 8 Device Configuration Code PAGE 3 3 3 5 7 10 11 CONTENTS PAGE 20 20 21 22 25 28 31 35 12 12 12 13 14 16 17 18 19 5 0 ELECTRICAL SPECIFICATIONS 5 1 Absolute Maximum Ratings 5 2 Capacitance 5 3 Timing Nomenclature 5 4 DC Characteristics (VCC e 3 3V g0 5V) 5 5 DC Characteristics (VCC e 5 0V g0 5V) 5 6 AC Characteristics Read Only Operations 5 7 Power-Up and Reset Timings 5 8 AC Characteristics for WE Controlled Command Write Operations 5 9 AC Characteristics for CE Controlled Command Write Operations 5 10 AC Characteristics for WE Controlled Page Buffer Write Operations 5 11 AC Characteristics for CE Controlled Page Buffer Write Operations 5 12 Erase and Word Byte Write Performance 6 0 MECHANICAL SPECIFICATIONS DEVICE NOMENCLATURE ADDITIONAL INFORMATION DATA SHEET REVISION HISTORY 36 39 42 44 45 47 48 48 48 2 VS28F016SV MS28F016SV FlashFile TM Memory The implementation of a new architecture with many enhanced features will improve the device operating characteristics and result in greater product reliability and ease of use The VS MS28F016SV incorporates SmartVoltage technology providing VCC operation at both 3 3V and 5 0V and program and erase capability at VPP e 12 0V or 5 0V Operating at VCC e 3 3V the VS MS28F016SV consumes approximately one-half the power consumption at 5 0V VCC while 5 0V VCC provides highest read performance capability VPP e 5 0V operation eliminates the need for a separate 12 0V converter while VPP e 12 0V maximizes write erase performance In addition to the flexible program and erase voltages the dedicated VPP gives complete code protection with VPP s VPPLK Depending on system design specifications the VS MS28F016SV is capable of supporting 80 ns access times with a VCC of 5 0V g5% and loading of 30 pF 85 ns access times with a VCC of 5 0V g10% and loading of 100 pF 120 ns access times with a VCC of 3 3V g5% and loading of 50 pF A 3 5 input pin configures the device's internal circuitry for optimal 3 3V or 5 0V Read Write operation A Command User Interface (CUI) serves as the system interface between the microprocessor or microcontroller and the internal memory operation Internal Algorithm Automation allows Byte Word Writes and Block Erase operations to be executed using a Two-Write command sequence to the CUI in the same way as the VE28F008 or M28F008 8-Mbit FlashFile memory A super-set of commands has been added to the basic VE28F008 or M28F008 command-set to achieve higher write performance and provide additional capabilities These new commands and features include 10 INTRODUCTION The documentation of the Intel VS MS28F016SV memory device includes this data sheet a detailed user's manual and a number of application notes all of which are referenced at the end of this data sheet The data sheet is intended to give an overview of the chip feature-set and of the operating AC DC specifications The 28F016SA (compatible with VS MS28F016SV) User's Manual provides complete descriptions of the user modes system interface examples and detailed descriptions of all principles of operation It also contains the full list of software algorithm flowcharts and a brief section on compatibility with the Intel VE28F008 and M28F008 1 1 Enhanced Features The VS MS28F016SV is backwards compatible with the VE28F008 and M28F008 and offers the following enhancements SmartVoltage Technology Selectable 5 0V or 12 0V VPP VPP Level Bit in Block Status Register Additional RY BY Configuration Pulse-On-Write Erase Additional Upload Device Information Command Feedback Device Revision Number Device Proliferation Code Device Configuration Code x8 x16 Architecture Block Locking 2 Page Buffers Instruction Queuing 1 2 Product Overview The VS MS28F016SV is a high-performance 16-Mbit (16 777 216-bit) block erasable non-volatile random access memory organized as either 1 Mword x 16 or 2 Mbyte x 8 The VS MS28F016SV includes thirty-two 64-KB (65 536 byte) blocks or thirty-two 32-KW (32 768 word) blocks A chip memory map is shown in Figure 3 Page Buffer Writes to Flash Command Queuing Capability Automatic Data Writes during Erase Software Locking of Memory Blocks Two-Byte Successive Writes in 8-bit Systems Erase All Unlocked Blocks 3 VS28F016SV MS28F016SV FlashFile TM Memory Writing of memory data is performed in either byte or word increments typically within 6 msec (12 0V VPP) b a 33% improvement over the VE28F008 or M28F008 A Block Erase operation erases one of the 32 blocks in about 1 0 sec (12 0V VPP) independent of the other blocks which is about a 65% improvement over the VE28F008 or M28F008 Each block can be written and erased a minimum of 100 000 cycles Systems can achieve one million Block Erase Cycles by providing wear-leveling algorithms and graceful block retirement These techniques have already been employed in many flash file systems and hard disk drive designs The VS MS28F016SV incorporates two Page Buffers of 256 bytes (128 words) each to allow page data writes This feature can improve a system write performance by up to 4 8 times over previous flash memory devices which have no Page Buffers All operations are started by a sequence of Write commands to the device Three Status Registers (described in detail later in this data sheet) and a RY BY output pin provide information on the progress of the requested operation While the VE28F008 or M28F008 requires an operation to complete before the next operation can be requested the VS MS28F016SV allows queuing of the next operation while the memory executes the current operation This eliminates system overhead when writing several bytes in a row to the array or erasing several blocks at the same time The VS MS28F016SV can also perform Write operations to one block of memory while performing Erase of another block The VS MS28F016SV provides selectable block locking to protect code or data such as Device Drivers PCMCIA card information ROM-Executable O S or Application Code Each block has an associated non-volatile lock-bit which determines the lock status of the block In addition the VS MS28F016SV has a master Write Protect pin (WP ) which prevents any modifications to memory blocks whose lock-bits are set The VS MS28F016SV contains three types of Status Registers to accomplish various functions A Global Status Register (GSR) which informs the system of command Queue status Page Buffer status and overall Write State Machine (WSM) status 32 Block Status Registers (BSRs) which provide block-specific status information such as the block lock-bit status The GSR and BSR memory maps for Byte-Wide and Word-Wide modes are shown in Figures 4 and 5 The VS MS28F016SV incorporates an open drain RY BY output pin This feature allows the user to OR-tie many RY BY pins together in a multiple memory configuration such as a Resident Flash Array Other configurations of the RY BY pin are enabled via special CUI commands and are described in detail in the 16-Mbit Flash Product Family User's Manual The VS MS28F016SV's Upload Device Information command is enhanced compared to the VE28F008 or M28F008 providing access to additional device information This command uploads the Device Revision Number Device Proliferation Code and Device Configuration Code The Device Proliferation Code for the VS MS28F016SV is 01H and the Device Configuration Code identifies the current RY BY configuration Section 4 4 documents the exact page buffer address locations for all uploaded information A subsequent Page Buffer Swap and Page Buffer Read command sequence is necessary to read the correct device information The VS MS28F016SV also incorporates a dual chipenable function with two input pins CE0 and CE1 These pins have exactly the same functionality as the regular chip-enable pin CE on the VE28F008 or M28F008 For minimum chip designs CE1 may be tied to ground and system logic may use CE0 as the chip enable input The VS MS28F016SV uses the logical combination of these two signals to enable or disable the entire chip Both CE0 and CE1 must be active low to enable the device If either one becomes inactive the chip will be disabled This feature along with the open drain RY BY pin allows the system designer to reduce the number of control pins used in a large array of 16-Mbit devices The BYTE pin allows either x8 or x16 read writes to the VS MS28F016SV BYTE at logic low selects 8-bit mode with address A0 selecting between low byte and high byte On the other hand BYTE A Compatible Status Register (CSR) which is 100% compatible with the VE28F008 or M28F008 FlashFile memory Status Register The CSR when used alone provides a straightforward upgrade capability to the VS MS28F016SV from a VE28F008- or M28F008-based design 4 VS28F016SV MS28F016SV FlashFile TM Memory at logic high enables 16-bit operation with address A1 becoming the lowest order address and address A0 is not used (don't care) A device block diagram is shown in Figure 1 The VS MS28F016SV is specified for a maximum access time of 80 ns (tACC) at 5 0V operation (4 75V to 5 25V) in either the SE1 or SE2 grades A corresponding maximum access time of 120 ns at 3 3V (3 15V to 3 45V) is achieved for reduced power consumption applications The VS MS28F016SV incorporates an Automatic Power Saving (APS) feature which substantially reduces the active current when the device is in static mode of operation (addresses not switching) In APS mode the typical ICC current is 1 mA at 5 0V (0 8 mA at 3 3V) A deep power-down mode of operation is invoked when the RP (called PWD on the VE28F008 or M28F008) pin transitions low This mode brings the device power consumption to less than 30 0 mA typically and provides additional write protection by acting as a device reset pin during power transitions A reset time of 500 ns (5 0V VCC operation) is required from RP switching high until outputs are again valid In the Deep Power-Down state the WSM is reset (any current operation will abort) and the CSR GSR and BSR registers are cleared A CMOS standby mode of operation is enabled when either CE0 or CE1 transitions high and RP stays high with all input control pins at CMOS levels In this mode the device typically draws an ICC standby current of 70 mA at 5V VCC 20 DEVICE PINOUT The VS MS28F016SV 56L-SSOP pinout configuration is shown in Figure 2 5 VS28F016SV MS28F016SV FlashFile TM Memory 271312 - 21 Figure 1 Block Diagram 6 VS28F016SV MS28F016SV FlashFile TM Memory 2 1 Lead Descriptions Symbol A0 Type INPUT Name and Function BYTE-SELECT ADDRESS Selects between high and low byte when device is in x8 mode This address is latched in x8 Data Writes Not used in x16 mode (i e the A0 input buffer is turned off when BYTE is high) WORD-SELECT ADDRESSES Select a word within one 64-Kbyte block A6-15 selects 1 of 1024 rows and A1-5 selects 16 of 512 columns These addresses are latched during Data Writes BLOCK-SELECT ADDRESSES Select 1 of 32 Erase blocks These addresses are latched during Data Writes Erase and Lock-Block operations LOW-BYTE DATA BUS Inputs data and commands during CUI write cycles Outputs array buffer identifier or status data in the appropriate read mode Floated when the chip is de-selected or the outputs are disabled HIGH-BYTE DATA BUS Inputs data during x16 Data-Write operations Outputs array buffer or identifier data in the appropriate read mode not used for Status Register reads Floated when the chip is de-selected or the outputs are disabled CHIP ENABLE INPUTS Activate the device's control logic input buffers decoders and sense amplifiers With either CE0 or CE1 high the device is de-selected and power consumption reduces to standby levels upon completion of any current Data-Write or Erase operations Both CE0 CE1 must be low to select the device All timing specifications are the same for both signals Device Selection occurs with the latter falling edge of CE0 or CE1 The first rising edge of CE0 or CE1 disables the device RESET POWER-DOWN RP low places the device in a Deep Power-Down state All circuits that consume static power even those circuits enabled in standby mode are turned off When returning from Deep Power-Down a recovery time of tPHQV at 5 0V VCC is required to allow these circuits to power-up When RP goes low any current or pending WSM operation(s) are terminated and the device is reset All Status Registers return to ready (with all status flags cleared) Exit from Deep Power-Down places the device in read array mode OUTPUT ENABLE Gates device data through the output buffers when low The outputs float to tri-state off when OE is high NOTE CEx overrides OE and OE overrides WE WRITE ENABLE Controls access to the CUI Page Buffers Data Queue Registers and Address Queue Latches WE is active low and latches both address and data (command or array) on its rising edge Page Buffer addresses are latched on the falling edge of WE A1 - A15 INPUT A16 - A20 INPUT DQ0 - DQ7 INPUT OUTPUT DQ8 - DQ15 INPUT OUTPUT CE0 CE1 INPUT RP INPUT OE INPUT WE INPUT 7 VS28F016SV MS28F016SV FlashFile TM Memory 2 1 Lead Descriptions Symbol RY BY Type OPEN DRAIN OUTPUT (Continued) Name and Function READY BUSY Indicates status of the internal WSM When low it indicates that the WSM is busy performing an operation RY BY floating indicates that the WSM is ready for new operations (or WSM has completed all pending operations) or erase is suspended or the device is in deep powerdown mode This output is always active (i e not floated to tri-state off when OE or CE0 CE1 are high) except if a RY BY Pin Disable command is issued WRITE PROTECT Erase blocks can be locked by writing a nonvolatile lockbit for each block When WP is low those locked blocks as reflected by the Block-Lock Status bits (BSR 6) are protected from inadvertent data writes or erases When WP is high all blocks can be written or erased regardless of the state ot the lock-bits The WP input buffer is disabled when RP transitions low (deep power-down mode) BYTE ENABLE BYTE low places device in x8 mode All data is then input or output on DQ0-7 and DQ8-15 float Address A0 selects between the high and low byte BYTE high places the device in x16 mode and turns off the A0 input buffer Address A1 then becomes the lowest order address 3 3 5 0 VOLT SELECT 3 5 high configures internal circuits for 3 3V operation 3 5 low configures internal circuits for 5 0V operation NOTE Reading the array with 3 5 high in a 5 0V system could damage the device Reference the power-up and reset timings (Section 5 7) for 3 5 switching delay to valid data WP INPUT BYTE INPUT 35 INPUT VPP SUPPLY WRITE ERASE POWER SUPPLY (12 0V g0 6V 5 0V g0 5V) For erasing memory array blocks or writing words bytes pages into the flash array VPP e 5 0V g0 5V eliminates the need for a 12V converter while connection to 1 2 0V g0 6V maximizes Write Erase Performance NOTE Successful completion of write and erase attempts is inhibited with VPP at or below 1 5V Write and erase attempts with VPP between 1 5V and 4 5V between 5 5V and 11 4V and above 12 6V produce spurious results and should not be attempted VCC SUPPLY DEVICE POWER SUPPLY (3 3V g0 45V 5 0V g0 5V 5 0 g0 25V) To switch 3 3V to 5 0V (or vice versa) first ramp VCC down to GND and then power to the new VCC voltage Do not leave any power pins floating GROUND FOR ALL INTERNAL CIRCUITRY Do not leave any ground pins floating NO CONNECT Lead may be driven or left floating GND NC SUPPLY 8 VS28F016SV MS28F016SV FlashFile TM Memory 271312 - 2 24mm x 13 5mm 0 8mm Lead Pitch Top View NOTE 56-Lead SSOP Mechanical Diagrams and dimensions are shown at the end of this data sheet Figure 2 SSOP Pinout Configuration 9 VS28F016SV MS28F016SV FlashFile TM Memory 30 MEMORY MAPS 271312 - 3 Figure 3 VS MS28F016SV Memory Maps (Byte-Wide and Word-Wide Modes) 10 VS28F016SV MS28F016SV FlashFile TM Memory 3 1 Extended Status Registers Memory Map 271312 - 4 271312 - 5 Figure 4 Extended Status Register Memory Map (Byte-Wide Mode) Figure 5 Extended Status Register Memory Map (Word-Wide Mode) 11 VS28F016SV MS28F016SV FlashFile TM Memory 40 BUS OPERATIONS COMMANDS AND STATUS REGISTER DEFINITIONS e VIH) WE VIH VIH X A1 X X X DQ0-15 DOUT High Z High Z RY BY X X X 4 1 Bus Operations for Word-Wide Mode (BYTE Mode Read Output Disable Standby Notes 127 167 167 RP VIH VIH VIH CE1 VIL VIL VIL VIH VIH X VIL VIL VIL CE0 VIL VIL VIH VIL VIH X VIL VIL VIL OE VIL VIH X Deep Power-Down Manufacturer ID Device ID Write 13 4 4 156 VIL VIH VIH VIH X VIL VIL VIH X VIH VIH VIL X VIL VIH X High Z 0089H 66A0H DIN VOH VOH VOH X 4 2 Bus Operations for Byte-Wide Mode (BYTE Mode Read Output Disable Standby Notes 127 167 167 RP VIH VIH VIH CE1 VIL VIL VIL VIH VIH X VIL VIL VIL CE0 VIL VIL VIH VIL VIH X VIL VIL VIL OE VIL e VIL) WE VIH VIH X A0 X X X DQ0-7 DOUT High Z High Z RY BY X X X VIH X Deep Power-Down Manufacturer ID Device ID Write 13 4 4 156 VIL VIH VIH VIH X VIL VIL VIH X VIH VIH VIL X VIL VIH X High Z 89H A0H DIN VOH VOH VOH X NOTES 1 X can be VIH or VIL for address or control pins except for RY BY which is either VOL or VOH 2 RY BY output is open drain When the WSM is ready Erase is suspended or the device is in deep power-down mode RY BY will be at VOH if it is tied to VCC through a resistor RY BY at VOH is independent of OE while a WSM operation is in progress 3 RP at GND g0 2V ensures the lowest deep power-down current 4 A0 and A1 at VIL provide device manufacturer codes in x8 and x16 modes respectively A0 and A1 at VIH provide device ID codes in x8 and x16 modes respectively All other addresses are set to zero 5 Commands for Erase Data Write or Lock-Block operations can only be completed successfully when VPP e VPPH1or VPP e VPPH2 6 While the WSM is running RY BY in level-mode (default) stays at VOL until all operations are complete RY BY goes to VOH when the WSM is not busy or in erase suspend mode 7 RY BY may be at VOL while the WSM is busy performing various operations For example a Status Register read during a Write operation 12 VS28F016SV MS28F016SV FlashFile TM Memory 4 3 VE28F008 and M28F008 Compatible Mode Command Bus Definitions Command Read Array Intelligent Identiier Read Compatible Status Register Clear Status Register Word Byte Write Alternate Word Byte Write Block Erase Confirm Erase Suspend Resume 1 2 3 Notes First Bus Cycle Oper Write Write Write Write Write Write Write Write ADDRESS AA e Array Address BA e Block Address IA e ldentitier Address WA e Write Address X e Don't Care Addr X X X X X X X X Data(4) xxFFH xx90H xx70H xx50H xx40H xx10H xx20H xxB0H Write Write Write Write WA WA BA X WD WD xxD0H xxD0H Second Bus Cycle Oper Read Read Read Addr AA IA X Data(4) AD ID CSRD DATA AD e Array Data CSRD e CSR Data ID e Identifier Data WD e Write Data NOTES 1 Following the Intelligent Identifier command two Read operations access the manutacturer and device signature codes 2 The CSR is automatically available after device enters data write erase or suspend operations 3 Clears CSR 3 CSR 4 and CSR 5 Also clears GSR 5 and all BSR 5 BSR 4 and BSR 2 bits See Status Register definitions 4 The upper byte of the data bus (DQ8 - 15) during command writes is a ``Don't Care'' in x16 operation of the device 13 VS28F016SV MS28F016SV FlashFile TM Memory 4 4 VS MS28F016SV Command Read Extended Status Register Page Buffer Swap Read Page Buffer Single Load to Page Buffer Sequential Load to Page Buffer Page Buffer Write to Flash Two-Byte Write Lock Block Confirm Upload Status Bits Confirm Upload Device Information Confirm Erase All Unlocked Blocks Confirm RY BY Enable to Level-Mode RY BY PulseOn-Write RY BY PulseOn-Erase RY BY Disable x8 x16 x8 x16 x8 Mode Performance Enhancement Command Bus Definitions Notes 1 7 First Bus Cycle Oper Write Write Write Write 4 6 10 Write Write Write Write Write Write 2 11 Write Write Addr X X X X X X X X X X X X Data(13) xx71H xx72H xx75H xx74H xxE0H xxE0H xx0CH xx0CH xxFBH xx77H xx97H xx99H Read Write Write Write Write Write Write Write Write Write PA PA X X A0 X A0 BA X X PD PD BCL WCL BC(L H) WCL WD(L H) xxD0H xxD0H xxD0H Write Write Write Write Write X X WA WA WA BCH WCH BC(H L) WCH WD(H L) Second Bus Cycle Oper Read Addr RA Data(13) GSRD BSRD Third Bus Cycle Oper Addr Data 4 5 6 10 3 4 9 10 4 5 10 3 Write 8 8 8 8 8 12 Write Write Write Write Write Write Write X X X X X X X X xxA7H xx96H xx96H xx96H xx96H xx96H xxF0H xx80H Write Write Write Write Write Write X X X X X X xxD0H xx01H xx02H xx03H xx04H xx05H RY BY PulseOn-Write Erase Sleep Abort ADDRESS BA e Block Address PA e Page Butter Address RA e Extended Register Address WA e Write Address X e Don't Care DATA AD e Array Data PD e Page Buffer Data BSRD e BSR Data GSRD e GSR Data WC (L H) e Word Count (Low High) BC (L H) e Byte Count (Low High) WD (L H) e Write Data (Low High) 14 VS28F016SV MS28F016SV FlashFile TM Memory NOTES 1 RA can be the GSR address or any BSR address See Figures 4 and 5 for Extended Status Register memory maps 2 Upon device power-up all BSR lock-bits come up locked The Upload Status Bits command must be written to reflect the actual lock-bit status 3 A0 is automatically complemented to load second byte of data BYTE must be at VIL A0 value determines which WD BC is supplied first A0 e 0 looks at the WDL BCL A0 e 1 looks at the WDH BCH 4 BCH WCH must be at 00H for this product because of the 256-byte (128-word) Page Buffer size and to avoid writing the Page Buffer contents to more than one 256-byte segment within an array block They are simply shown for future Page Buffer expandability 5 In x16 mode only the lower byte DQ0-7 is used for WCL and WCH The upper byte DQ8-15 is a don't care 6 PA and PD (whose count is given in cycles 2 and 3) are supplied starting in the fourth cycle which is not shown 7 This command allows the user to swap between available Page Buffers (0 or 1) 8 These commands reconfigure RY BY output to one of two pulse-modes or enable and disable the RY BY function 9 Write address WA is the Destination address in the flash array which must match the Source address in the Page Buffer Refer to the 16-Mbit Flash Product Family User's Manual 10 BCL e 00H corresponds to a byte count of 1 Similarly WCL e 00H corresponds to a word count of 1 11 After writing the Upload Device Information command and the Confirm command the following information is output at Page Buffer addresses specified below Address Information 06H 07H (Byte Mode) Device Revision Number 03H (Word Mode) Device Revision Number 1EH (Byte Mode) Device Configuration Code Device Configuration Code 0FH (DQ0 - 7) (Word Mode) 1FH (Byte Mode) Device Proliferation Code (01H) Device Proliferation Code (01H) 0FH (DQ8 - 15) (Word Mode) A page buffer swap followed by a page buffer read sequence is necessary to access this information The contents of all other Page Buffer locations after the Upload Device Information command is written are reserved for future implementation by Intel Corporation See Section 4 8 for a description of the Device Configuration Code This code also corresponds to data written to the 28F016SV after writing the RY BY Reconfiguration command 12 To ensure that the 28F0165V's power consumption during Sleep Mode reaches the deep power-down current level the system also needs to de-select the chip by taking either or both CE0 or CE1 high 13 The upper byte of the data bus (DQ8 - 15) during command wntes is a Don't Care in x16 operation of the device 15 VS28F016SV MS28F016SV FlashFile TM Memory 4 5 Compatible Status Register WSMS 7 ESS 6 ES 5 DWS 4 VPPS 3 R 2 R 1 R 0 CSR 7 e WRITE STATE MACHINE STATUS 1 e Ready 0 e Busy CSR 6 1 0 CSR 5 1 0 CSR 4 1 0 CSR 3 1 0 e e e e e e e e e e e e NOTES RY BY output or WSMS bit must be checked to determine completion of an operation (Erase Erase Suspend or Data Write) before the appropriate Status bit (ESS ES or DWS) is checked for success The VPPS bit unlike an A D converter does not provide continuous indication of VPP level The WSM interrogates VPP's level only after the Data-Write or Erase command sequences have been entered and informs the system if VPP has not been switched on VPPS is not guaranteed to report accurate feedback between VPPLK(max) and VPPH1(min) and between VPPH1(max) and VPPH2(min) and above VPPH2(max) CSR 2-0 e RESERVED FOR FUTURE ENHANCEMENTS These bits are reserved for future use mask them out when polling the CSR ERASE-SUSPEND STATUS Erase Suspended Erase In Progress Completed ERASE STATUS Error In Block Erasure Successful Block Erase DATA-WRITE STATUS Error in Data Write Data Write Successful VPP STATUS VPP Error Detect Operation Abort VPP OK If DWS and ES are set to ``1'' during an erase attempt an improper command sequence was entered Clear the CSR and attempt the operation again 16 VS28F016SV MS28F016SV FlashFile TM Memory 4 6 Global Status Register WSMS 7 OSS 6 DOS 5 DSS 4 QS 3 PBAS 2 PBS 1 PBSS 0 GSR 7 e WRITE STATE MACHINE STATUS 1 e Ready 0 e Busy GSR 6 e OPERATION SUSPEND STATUS 1 e Operation Suspended 0 e Operation in Progress Completed GSR 5 e DEVICE OPERATION STATUS 1 e Operation Unsuccessful 0 e Operation Successful or Currently Running GSR 4 e DEVICE SLEEP STATUS 1 e Device in Sleep 0 e Device Not in Sleep MATRIX 5 4 0 0 e Operation Successful or Currently Running 0 1 e Device in Sleep mode or Pending Sleep 1 0 e Operation Unsuccessful 1 1 e Operation Unsuccessful or Aborted GSR 3 1 0 GSR 2 1 0 GSR 1 1 0 e e e e e e e e e NOTES 1 RY BY output or WSMS bit must be checked to determine completion of an operation (Block Lock Suspend any RY BY reconfiguration Upload Status Bits Erase or Data Write) before the appropriate Status bit (OSS or DOS) is checked for success If operation currently running then GSR 7 e 0 If device pending sleep then GSR 7 e 0 Operation aborted Unsuccessful due to Abort command QUEUE STATUS Queue Full Queue Available PAGE BUFFER AVAILABLE STATUS One or Two Page Buffers Available No Page Buffer Available PAGE BUFFER STATUS Selected Page Buffer Ready Selected Page Buffer Busy The device contains two Page Buffers Selected Page Buffer is currently busy with WSM operation GSR 0 e PAGE BUFFER SELECT STATUS 1 e Page Buffer 1 Selected 0 e Page Buffer 0 Selected NOTE 1 When multiple operations are queued checking BSR 7 only provides indication of completion for that particular block GSR 7 provides indication when all queued operations are completed 17 VS28F016SV MS28F016SV FlashFile TM Memory 4 7 Block Status Register BS 7 BLS 6 BOS 5 BOAS 4 QS 3 VPPS 2 VPPL 1 R 0 BSR 7 e BLOCK STATUS 1 e Ready 0 e Busy BLOCK LOCK STATUS Block Unlocked for Write Erase Block Locked for Write Erase BLOCK OPERATION STATUS Operation Unsuccessful Operation Successful or Currently Running BSR 4 e BLOCK OPERATION ABORT STATUS 1 e Operation Aborted 0 e Operation Not Aborted MATRIX 5 4 0 0 e Operation Successful or Currently Running 0 1 e Not a Valid Combination 1 0 e Operation Unsuccessful 1 1 e Operation Aborted BSR 3 e QUEUE STATUS 1 e Queue Full 0 e Queue Available BSR 2 e VPP STATUS 1 e VPP Error Detect Operation Abort 0 e VPP OK BSR 1 e VPP LEVEL 1 e VPP Detected at 5 0V g10% 0 e VPP Detected at 12 0V g5% e e e e e e NOTES 1 RY BY output or BS bit must be checked to determine completion of an operation (Block Lock Suspend Erase or Data Write) before the appropriate Status bits (BOS BLS) is checked for success BSR 6 1 0 BSR 5 1 0 The BOAS bit will not be set until BSR 7 e 1 Operation halted via Abort command BSR 1 is not guaranteed to report accurate feedback between the VPPH1 and VPPH2 voltage ranges Writes and erases with VPP between VPPLK(max) and VPPH1 (min) between VPPH1(max) and VPPH2(min) and above VPPH2(max) produce spurious results and should not be attempted BSR 1 was a RESERVED bit on the 28F016SA BSR 0 e RESERVED FOR FUTURE ENHANCEMENTS This bit is reserved for future use mask it out when polling the BSRs NOTE 1 When multiple operations are queued checking BSR 7 only provides indication of completion for that particular block GSR 7 provides indication when all queued operations are completed 18 VS28F016SV MS28F016SV FlashFile TM Memory 4 8 Device Configuration Code R 7 R 6 R 5 R 4 R 3 RB2 2 RB1 1 RB0 0 NOTES DCC 2-DCC 0 e RY BY CONFIGURATION (RB2-RB0) Undocumented combinations of RB2-RB0 are reserved by Intel Corporation for future 001 e Level Mode (Default) implementations and should not be used 010 e Pulse-On-Write 011 e Pulse-On-Erase 100 e RY BY Disabled 101 e Pulse-On-Write Erase DCC 7-DCC 3 e RESERVED FOR FUTURE ENHANCEMENTS These bits are reserved for future use mask them out when reading the Device Configuration Code Set these bits to ``0'' when writing the desired RY BY configuration to the device 19 VS28F016SV MS28F016SV FlashFile TM Memory 50 ELECTRICAL SPECIFICATIONS 5 1 Absolute Maximum Ratings Temperature Under Bias SE1 SE2 Storage Temperature b 55 C to a 125 C b 40 C to a 125 C b 65 to a 125 C NOTICE This data sheet contains information on products in the sampling and initial production phases of development The specifications are subject to change without notice Verify with your local Intel Sales office that you have the latest data sheet before finalizing a design WARNING Stressing the device beyond the ``Absolute Maximum Ratings'' may cause permanent damage These are stress ratings only Operation beyond the ``Operating Conditions'' is not recommended and extended exposure beyond the ``Operating Conditions'' may affect device reliability VCC e 3 3V g0 15V Systems(4) Sym TCSE2 TCSE1 VCC VPP V I IOUT Parameter Operating Temperature SE2 Operating Temperature SE1 VCC with Respect to GND VPP Supply Voltage with Respect to GND Voltage on any Pin (except VCC VPP) with Respect to GND Current into any Non-Supply Pin Output Short Circuit Current 1 12 15 5 3 Notes Min b 40 b 55 b0 2 b0 2 b0 5 Max a 125 a 125 Units C C V V V mA mA Test Conditions 70 14 0 VCC a0 5 g30 100 VCC e 5 0V g0 5V VCC e 5 0V g0 25V Systems(4 5) Sym TCSE2 TCSE1 VCC VPP V I IOUT Parameter Operating Temperature SE2 Operating Temperature SE1 VCC with Respect to GND VPP Supply Voltage with Respect to GND Voltage on any Pin (except VCC VPP) with Respect to GND Current into any Non-Supply Pin Output Short Circuit Current 1 12 15 5 3 Notes Min b 40 b 55 b0 2 b0 2 b2 0 Max a 125 a 125 Units C C V V V mA mA Test Conditions 70 14 0 70 g30 100 NOTES 1 Minimum DC voltage is b0 5V on input output pins During transitions this level may undershoot to b2 0V for periods k 20 ns Maximum DC voltage on input output pins is VCC a 0 5V which during transitions may overshoot to VCC a 2 0V for periods k20 ns 2 Maximum DC voltage on VPP may overshoot to a 14 0V for periods k20 ns 3 Output shorted for no more than one second No more than one output shorted at a time 4 AC specifications are valid at both voltage ranges See DC Characteristics tables for voltage range-specific specifications 5 This specification also applies to pin marked ``NC'' 6 5% VCC specifications refer to the VS MS28F016SV-80 in its high speed test configuration 20 VS28F016SV MS28F016SV FlashFile TM Memory 5 2 Capacitance For a 3 3V g0 15V System Sym CIN COUT CLOAD Parameter Capacitance Looking into an Address Control Pin Capacitance Looking into an Output Pin Load Capacitance Driven by Outputs for Timing Specifications Equivalent Load Timing Circuit Notes 1 1 12 Typ 6 8 Max 8 12 50 25 Units pF pF pF ns Test Conditions TA e 25 C f e 1 0 MHz TA e 25 C f e 1 0 MHz For VCC e 3 3V g0 15V 50X transmission line delay For a 5 0V System Sym CIN COUT CLOAD Parameter Capacitance Looking into an Address Control Pin Capacitance Looking into an Output Pin Load Capacitance Driven by Outputs for Timing Specifications Equivalent Testing Load Circuit for VCC g10% Equivalent Testing Load Circuit for VCC g5% Notes 1 1 12 Typ 6 8 Max 8 12 100 30 25 25 Units pF pF pF pF ns ns Test Conditions TA e 25 C f e 1 0 MHz TA e 25 C f e 1 0 MHz For VCC e 5 0V g0 5V For VCC e 5 0V g0 25V 25X transmission line delay 85X transmission line delay NOTES 1 Sampled not 100% tested Guaranteed by design 2 To obtain iBIS models for the VS MS28F016SV please contact your local Intel Distribution Sales Office 21 VS28F016SV MS28F016SV FlashFile TM Memory tCE tOE tACC tAS Each timing parameter consists of 5 characters Some common examples are defined as follows tDH tELQV time(t) from CE (E) going low (L) to the outputs (Q) becoming valid (V) tGLQV time(t) from OE (G) going low (L) to the outputs (Q) becoming valid (V) tAVQV time(t) from address (A) valid (V) to the outputs (Q) becoming valid (V) tAVWH time(t) from address (A) valid (V) to WE (W) going high (H) tWHDX time(t) from WE (W) going high (H) to when the data (D) can become undefined (X) Pin States H L V X Z High Low Valid Driven but not Necessarily Valid High Impedance 5 3 Timing Nomenclature All 3 3V system timings are measured from where signals cross 1 5V For 5 0V systems use the standard JEDEC cross point definitions Pin Characters A D Q E F G W P R V Y 5V 3V Address Inputs Data Inputs Data Outputs CE (Chip Enable) (Byte Enable) BYTE OE WE RP (Output Enable) (Write Enable) (Deep Power-Down Pin) (Ready Busy) RY BY Any Voltage Level 35 Pin VCC at 4 5V Minimum VCC at 3 15V Minimum 22 VS28F016SV MS28F016SV FlashFile TM Memory 271312 - 6 AC test inputs are driven at VOH (2 4 VTTL) for a Logic ``1'' and VOL (0 45 VTTL) for a Logic ``0 '' Input timing begins at VIH (2 0 VTTL) and VIL (0 8 VTTL) Output timing ends at VIH and VIL Input rise and fall times (10% to 90%) k10 ns Figure 6 Transient Input Output Reference Waveform for VCC e 5 0V g10% (Standard Testing Configuration) 271312 - 7 AC test inputs are driven at 3 15V for a Logic ``1'' and 0 0V for a Logic ``0 '' Input timing begins and output timing ends at 1 5V Input rise and fall times (10% to 90%) k10 ns Figure 7 Transient Input Output Reference Waveform (VCC e 3 3V g0 15V) High Speed Reference Waveform (VCC e 5 0V g5%) NOTE 1 Testing characteristics for VS MS28F016SV-085 (Standard Testing Configuration) and VS MS28F016SV-100 23 VS28F016SV MS28F016SV FlashFile TM Memory 2 5 ns of 25X Transmission Line Total Capacitance e 100 pF 271312 - 8 Figure 8 Transient Equivalent Testing Load Circuit (VCC e 5 0V g10%) 2 5 ns of 50X Transmission Line Total Capacitance e 50 pF 271312 - 9 Figure 9 Transient Equivalent Testing Load Circuit (VCC e 3 3V g0 15V) 2 5 ns of 83X Transmission Line Total Capacitance e 30 pF 271312 - 10 Figure 10 High Speed Transient Equivalent Testing Load Circuit (VCC e 5 0V g5%) 24 VS28F016SV MS28F016SV FlashFile TM Memory 5 4 DC Characteristics VCC e 3 3V g0 15V TCSE2 e b 40 C to a 125 C TCSE1 e b 55 C to a 125 C Sym ILI ILO ICCS Parameter Input Load Current Output Leakage Current VCC Standby Current Notes 1 1 15 Min Max g1 Units mA mA mA Test Conditions VCC e VCC Max VIN e VCC or GND VCC e VCC Max VOUT e VCC or GND VCC e VCC Max CE0 CE1 RP e VCC g0 2V BYTE WP 3 5 e VCC g0 2V or GND g0 2V VCC e VCC Max CE0 CE1 RP e VIH BYTE WP 3 5 e VIH or VIL RP e GND g0 2V BYTE e VCC g0 2V or GND g0 2V VCC e VCC Max CMOS CE0 CE1 e GND g0 2V BYTE e GND g0 2V or VCC g0 2V Inputs e GND g0 2V or VCC g0 2V TTL CE0 CE1 e VIL BYTE e VIL or VIH INPUTS e VIL or VIH f e 8 MHz IOUT e 0 mA VCC e VCC Max CMOS CE0 CE1 e GND g0 2V BYTE e GND g0 2V or VCC g0 2V Inputs e GND g0 2V or VCC g0 2V TTL CE0 CE1 e VIL BYTE e VIL or VIH INPUTS e VIL or VIH f e 4 MHz IOUT e 0 mA g10 130 4 mA ICCD VCC Deep PowerDown Current VCC Read Current 1 50 mA ICCR1 145 60 mA ICCR2 VCC Read Current 1456 40 mA 25 VS28F016SV MS28F016SV FlashFile TM Memory 5 4 DC Characteristics Sym ICCW Parameter VCC Write Current (Continued) VCC e 3 3V g0 3V TCSE2 e b 40 C to a 125 C TCSE1 e b 55 C to a 125 C Notes 16 Min Max 12 17 ICCE VCC Block Erase Current 16 12 17 ICCES IPPS IPPR IPPD IPPW VCC Erase Suspend Current VPP Standby Read Current VPP Deep PowerDown Current VPP Write Current 12 1 6 g100 Units mA mA mA mA mA mA mA mA mA mA mA mA mA V V V Test Conditions Word Byte Write in Progress VPP e 12 0V g5% Word Byte Write in Progress VPP e 5 0V g10% Block Erase in Progress VPP e 12 0V g5% Block Erase in Progress VPP e 5 0V g10% CE0 CE1 e VIH Block Erase Suspended VPP s VCC VPP l VCC RP e GND g0 2V 200 1 1 50 15 25 VPP e 12 0V g5% Word Byte Write in Progress VPP e 5 0V g10% Word Byte Write in Progress VPP e 12 0V g5% Block Erase in Progress VPP e 5 0V g10% Block Erase in Progress VPP e VPPH1 or VPPH2 Block Erase Suspended IPPE VPP Erase Current 1 10 20 IPPES VIL VIH VPP Erase Suspend Current Input Low Voltage Input High Voltage 1 b0 3 200 08 VCC 20 a 03 VOL Output Low Voltage 04 VCC e VCC Min and IOL e 4 mA 26 VS28F016SV MS28F016SV FlashFile TM Memory 5 4 DC Characteristics Sym VOH1 VOH2 VPPLK VPPH1 Parameter Output High Voltage (Continued) VCC e 3 3V g0 15V TCSE2 e b 40 C to a 125 C TCSE1 e b 55 C to a 125 C Notes Min 24 VCC b 0 2 VPP Erase Write Lock Voltage VPP during Write Erase Operations VPP during Write Erase Operations VCC Erase Write Lock Voltage 3 3 00 45 18 55 Max Units V V V V Test Conditions IOH e b 2 0 mA VCC e VCC Min IOH e b 100 mA VCC e VCC Min VPPH2 3 11 4 12 6 V VLKO 18 V NOTES 1 All currents are in RMS unless otherwise noted These currents are valid for all product versions (package and speeds) 2 ICCES is specified with the device de-selected If the device is read while in erase suspend mode current draw is the sum of ICCES and ICCR 3 Block Erases Word Byte Writes and Lock Block operations are inhibited when VPP s VPPLK and not guaranteed in the ranges between VPPLK(max) and VPPH1(min) between VPPH1(max) and VPPH2(min) and above VPPH2(max) 4 Automatic Power Savings (APS) reduces ICCR to less than 3 mA in static operation 5 CMOS Inputs are either VCC g0 2V or GND g0 2V TTL Inputs are either VIL or VIH 6 Sampled but not 100% tested Guaranteed by design 27 VS28F016SV MS28F016SV FlashFile TM Memory 5 5 DC Characteristics VCC e 5 0V g 0 5V 5 0V g 0 25V TCSE2 e b 40 C to a 125 C TCSE1 e b 55 C to a 125 C Sym ILI ILO ICCS Parameter Input Load Current Output Leakage Current VCC Standby Current Notes 1 1 15 Min Max g1 Units mA mA mA Test Conditions VCC e VCC Max VIN e VCC or GND VCC e VCC Max VIN e VCCor GND VCC e VCC Max CE0 CE1 RP e VCC g 0 2V BYTE WP e VCC g 0 2V or GND g0 2V VCC e VCC Max CE0 CE1 RP e VIH BYTE WP 3 5 e VIH or VIL RP e GND g0 2V BYTE e VCC g0 2V or GND g0 2V VCC e VCC Max CMOS CE0 CE1 e GND g 0 2V BYTE e GND g0 2V or VCC g0 2V Inputs e GND g0 2V or VCC g0 2V TTL CE0 CE1 e VIL BYTE e VIL or VIH Inputs e VIL or VIH f e 10 MHz IOUT e 0 mA VCC e VCC Max CMOS CE0 CE1 e GND g 0 2V BYTE e GND g0 2V or VCC g0 2V Inputs e GND g0 2V or VCC g0 2V TTL CE0 CE1 e VIL BYTE e VIL or VIH Inputs e VIL or VIH f e 5 MHz IOUT e 0 mA g10 130 4 mA ICCD VCC Deep PowerDown Current VCC Read Current 1 50 mA ICCR1 145 135 mA ICCR2 VCC Read Current 1456 90 mA 28 VS28F016SV MS28F016SV FlashFile TM Memory 5 5 DC Characteristics Sym ICCW Parameter VCC Write Current (Continued) VCC e 5 0V g 0 5V 5 0V g 0 25V TCSE2 e b 40 C to a 125 C TCSE1 e b 55 C to a 125 C Notes 16 Min Max 35 40 ICCE VCC Block Erase Current 16 25 30 ICCES IPPS IPPR IPPD IPPW VCC Erase Suspend Current VPP Standby Read Current VPP Deep PowerDown Current VPP Write Current 12 1 10 g100 Units mA mA mA mA mA mA mA mA mA mA mA mA mA V V Test Conditions Word Byte in Progress VPP e 12 0V g5% Word Byte in Progress VPP e 5 0V g10% Block Erase in Progress VPP e 12 0V g5% Block Erase in Progress VPP e 5 0V g10% CE0 CE1 e VIH Block Erase Suspended VPP s VCC VPP l VCC RP e GND g0 2V 200 1 16 50 12 22 VPP e 12 0V g5% Word Byte Write in Progress VPP e 5 0V g10% Word Byte Write in Progress VPP e 12 0V g5% Block Erase in Progress VPP e 5 0V g10% Block Erase in Progress VPP e VPPH1 or VPPH2 Block Erase Suspended IPPE VPP Block Erase Current 16 10 20 IPPES VIL VIH VPP Erase Suspend Current Input Low Voltage Input High Voltage 1 6 6 b0 5 200 08 VCC a0 5 20 29 VS28F016SV MS28F016SV FlashFile TM Memory 5 5 DC Characteristics Sym VOL VOH1 VOH2 VPPLK VPPH1 Parameter Output Low Voltage Output High Voltage (Continued) VCC e 5 0V g 0 5V 5 0V g 0 25V TCSE2 e b 40 C to a 125 C TCSE1 e b 55 C to a 125 C Notes 6 6 6 VPP Write Erase Lock Voltage VPP during Write Erase Operations VPP during Write Erase Operations VCC Write Erase Lock Voltage 36 0 85 VCC VCC b0 4 Min Max 0 45 Units V V Test Conditions VCC e VCC Min IOL e 5 8 mA IOH e b 2 5 mA VCC e VCC Min IOH e b 100 mA VCC e VCC Min 00 45 18 55 V V VPPH2 11 4 12 6 V VLKO 18 V NOTES 1 All currents are in RMS unless otherwise noted These currents are valid for all product versions (package and speeds) 2 ICCES is specified with the device de-selected If the device is read while in erase suspend mode current draw is the sum of ICCESand ICCR 3 Block Erases Word Byte Writes and Lock Block operations are inhibited when VPP s VPPLK and not guaranteed in the ranges between VPPLK(max) and VPPH1(min) between VPPH1(max) and VPPH2(min) and above VPPH2(max) 4 Automatic Power Saving (APS) reduces ICCR to less than 1 mA in Static operation 5 CMOS Inputs are either VCC g0 2V or GND g0 2V TTL Inputs are either VIL or VIH 6 Sampled not 100% tested Guaranteed by design 30 VS28F016SV MS28F016SV FlashFile TM Memory 5 6 AC Characteristics Read Only Operations(1) Versions Units ns 120 27 120 620 2 37 37 3 3 37 3 3 37 0 120 30 5 0 30 0 50 45 ns ns ns ns ns ns ns ns ns ns ns ns VCC e 3 3V g0 15V TCSE2 e b 40 C to a 125 C TCSE1 e b 55 C to a 125 C Load e 50 pF Sym tAVAV tAVQV tELQV tPHQV tGLQV tELQX tEHQZ tGLQX tGHQZ tOH tFLQV tFHQV tFLQZ tELFL tELFH Parameter Read Cycle Time Address to Output Delay (TACC) CE RP OE CE CE OE OE to Output Delay (TCE) High to Output Delay to Output Delay (TOE) to Output in Low Z to Output in High Z to Output in Low Z to Output in High Z Notes Min 120 Max Output Hold from Address CE or OE Change Whichever Occurs First BYTE BYTE CE to Output Delay Low to Output in High Z High or Low Low to BYTE Extended Status Register Reads Sym tAVEL tAVGL Parameter Address Setup to CE Address Setup to OE Going Low Going Low Notes 3789 379 Min 0 0 Max Units ns ns 31 VS28F016SV MS28F016SV FlashFile TM Memory 5 6 AC Characteristics Read Only Operations(1) (Continued) VCC e 5 0V g0 25V TCSE2 e b 40 C to a 125 C TCSE1 e b 55 C to a 125 C Load e 30 pF VCC e 5 0V g0 5V TCSE2 e b 40 C to a 125 C TCSE1 e b 55 C to a 125 C Load e 100 pF Versions(4) Sym tAVAV tAVQV tELQV tPHQV tGLQV tELQX tEHQZ tGLQX tGHQZ tOH Parameter Read Cycle Time Address to Output Delay (TACC) CE to Output Delay (TCE) RP to Output Delay OE to Output Delay (TOE) CE to Output in Low Z CE to Output in High Z OE to Output in Low Z OE to Output in High Z Output Hold from Address CE or OE Change Whichever Occurs First BYTE Delay to Output 2 3 3 3 3 3 0 0 25 0 0 25 0 30 0 2 Notes VS MS28F016SV-85 VCC g5%(5) Min 80 80 80 400 30 0 30 0 35 Max VS MS28F016SV-85 VCC g10%(6) Min 85 85 85 480 35 0 35 Max VS MS28F016SV-100 VCC g 10% Min 100 100 100 480 40 Max ns ns ns ns ns ns ns ns ns ns Unit tFLQV tFHQV tFLQZ tELFL tELFH 3 3 3 80 25 5 85 30 5 100 35 5 ns ns ns BYTE Low to Output in High Z CE Low to BYTE High or Low Extended Status Register Reads Sym tAVEL tAVGL Parameter Address Setup to CE Low Address Setup to OE Low Going Going Notes 3789 379 Min 0 0 Max Min 0 0 Max Min 0 0 Max Unit ns ns 32 VS28F016SV MS28F016SV FlashFile TM Memory NOTES 1 See AC Input Output Reference Waveforms for timing measurements Figures 6 and 7 2 OE may be delayed up to tELQV - tGLQV after the falling edge of CE without impacting tELQV 3 Sampled not 100% tested Guaranteed by design 4 Device speeds are defined as 80 85 100 ns at VCC e 5 0V equivalent to 120 ns at VCC e 3 3V 5 See the high speed AC Input Output Reference Waveforms and AC Testing Load Circuit 6 See the standard AC Input Output Reference Waveforms and AC Testing Load Circuit 7 CEx is defined as the latter of CE0 or CE1 going low or the f 8 This timing parameter is used to latch the correct BSR data onto the outputs 9 The address setup requirement for Extended Status Register reads must only be met referenced to the falling edge of the last control signal to become active (CE0 CE1 or OE ) For example if CE0 or CE1 are activated prior to OE for an Extended Status Register read specification tAVGL must be met On the other hand if either CE0 or CE1 (or both) are activated after OE specification tAVEL must be referenced 271312 - 11 NOTE CEx is defined as the latter of CE0 or CE1 going low or the first of CE0 or CE1 going high Figure 11 Read Timing Waveforms 33 VS28F016SV MS28F016SV FlashFile TM Memory 271312 - 12 NOTE CEx is defined as the latter of CE0 or CE1 going low or the first of CE0 or CE1 going high Figure 12 BYTE Timing Waveforms 34 VS28F016SV MS28F016SV FlashFile TM Memory 5 7 Power-Up and Reset Timings 271312 - 22 Figure 13 VCC Power-Up and RP Symbol tPLYL tPLYH tYLPH tYHPH tPL5V tPL3V tPHEL3 tPHEL5 tAVQV tPHQV RP 35 Low to 3 5 Parameter Low (High) High Reset Waveforms Notes Min 0 1 2 1 1 3 3 2 0 405 330 70 400 Max Unit ms ms ms ns ns ns ns Low (High) to RP RP Low to VCC at 4 5V minimum (to VCC at 3 0V min or 3 6V max) RP RP High to CE High to CE Low (3 3V VCC) Low (5V VCC) Address Valid to Data Valid for VCC e 5V g10% RP High to Data Valid for VCC e 5V g10% NOTES CE0 CE1 and OE are switched low after Power-Up 1 The tYLPH and or tYHPH times must be strictly followed to guarantee all other read and write specifications for the VS MS28F016SV 2 The power supply may start to switch concurrently with RP going low 3 The address access time and RP high to data valid time are shown for 5 0V VCC operation of the 28F016SV-085 (Standard Test Configuration) Refer to the AC Chracteristics Read Only Operations for 3 3V VCC and 5 0V VCC (High Speed Test Configuration) values 35 VS28F016SV MS28F016SV FlashFile TM Memory 5 8 AC Characteristics for WE Versions Sym tAVAV tVPWH(1 2) tPHEL tELWL tAVWH tDVWH tWLWH tWHDX tWHAX tWHEH tWHWL tGHWL tWHRL tRHPL tPHWL tWHGL tQVVL(1 2) tWHQV(1) tWHQV(2) Parameter Write Cycle Time VPP Setup to WE RP CE Setup to CE Setup to WE Controlled Command Write Operations(1) Unit ns ns ns ns ns ns ns ns ns ns ns ns 100 0 480 95 3 3 4 5 11 34 0 5 03 10 ns ns ns ns ms ms sec VCC e 3 3V g0 15V TCSE2 e b 40 C to a 125 C TCSE1 e b 55 C to a 125 C Load e 50 pF Notes Min 120 Going High Going Low Going Low Going High 3 37 37 26 26 100 480 10 75 75 75 High High 2 2 37 10 10 10 45 3 3 3 3 0 Max Address Setup to WE Data Setup to WE WE Pulse Width Going High Data Hold from WE Address Hold from WE CE WE Hold from WE High Pulse Width High Read Recovery before Write WE High to RY BY Going Low RP Hold from Valid Status Register (CSR GSR BSR) Data and RY BY High RP High Recovery to WE Going Low Write Recovery before Read VPP Hold from Valid Status Register (CSR GSR BSR) Data and RY BY High Duration of Word Byte Write Operation Duration of Block Erase Operation 36 VS28F016SV MS28F016SV FlashFile TM Memory 5 8 AC Characteristics for WE Controlled Command Write Operations(1) (Continued) VCC e 5 0V g0 25V TCSE2 e b 40 C to a 125 C TCSE1 e b 55 C to a 125 C Load e 30 pF VCC e 5 0V g0 5V TCSE2 e b 40 C to a 125 C TCSE1 e b 55 C to a 125 C Load e 100 pF Versions Sym tAVAV tVPWH(1) tVPWH(2) tPHEL Parameter Write Cycle Time VPP Setup to WE Going High RP Setup to CE Going Low CE Setup to WE Going Low Address Setup to WE Going High Data Setup to WE Going High WE Pulse Width Data Hold from WE High Address Hold from WE High CE Hold from WE High WE Pulse Width High Read Recovery before Write WE High to RY BY Going Low RP Hold from Valid Status Register (CSR GSR BSR) Data and RY BY High 3 2 3 Notes VS MS28F016SV-85 VCC g5% Min 80 100 Max VS MS28F016SV-85 VCC g10% Min 85 100 Max VS MS28F016SV-100 VCC g10% Min 100 100 Max ns ns Unit 37 480 480 480 ns tELWL 37 0 0 0 ns tAVWH 26 50 50 50 ns tDVWH 26 50 50 50 ns tWLWH tWHDX 50 10 60 10 70 10 ns ns tWHAX 2 10 10 10 ns tWHEH 37 10 10 10 ns tWHWL tGHWL 30 0 30 0 30 0 ns ns tWHRL 3 100 100 100 ns tRHPL 3 0 0 0 ns 37 VS28F016SV MS28F016SV FlashFile TM Memory 5 8 AC Characteristics for WE VCC e 5 0V g0 25V TCSE2 e b 40 C to a 125 C TCSE1 e b 55 C to a 125 C Load e 30 pF VCC e 5 0V g0 5V TCSE2 e b 40 C to a 125 C TCSE1 e b 55 C to a 125 C Load e 100 pF (Continued) Versions Sym tPHWL Parameter RP High Recovery to WE Going Low Write Recovery before Read VPP Hold from Valid Status Register (CSR GSR BSR) Data and RY BY High Duration of Word Byte Write Operation Duration of Block Erase Operation 3 Notes 3 VS MS28F016SV-85 VCC g5% Min 1 Max VS MS28F016SV-85 VCC g10% Min 1 Max Controlled Command Write Operations(1) VS MS28F016SV-100 VCC g10% Min 1 Max Unit ms tWHGL 60 65 70 ns tQVVL(1) tQVVL(2) 0 0 0 ms tWHQV(1) 3 4 5 11 45 45 45 ms tWHQV(2) 34 03 10 03 10 03 10 sec NOTES 1 Read timings during write and erase are the same as for normal read 2 Refer to command definition tables for valid address and data values 3 Sampled not 100% tested Guaranteed by design 4 Write Erase durations are measured to valid Status Register (CSR) Data VPP e 12 0V g0 6V 5 Word Byte Write operations are typically performed with 1 Programming Pulse 6 Address and Data are latched on the rising edge of WE for all Command Write operations 7 CEx is defined as the latter of CE0 or CE1 going low or the first of CE0 or CE1 going high 8 Device speeds are defined as 80 85 100 ns at VCC e 5 0V equivalent to 120 ns at VCC e 3 3V 9 See the high speed AC Input Output Reference Waveforms and AC Testing Load Circuit 10 See the standard AC Input Output Reference Waveforms and AC Testing Load Circuit 11 The TBD information will be available in a technical paper Please contact Intel's Application Hotline or your local sales office for more information 38 VS28F016SV MS28F016SV FlashFile TM Memory 271312 - 23 NOTES 1 This address string depicts data write erase cycles with corresponding verification via ESRD 2 This address string depicts data write erase cycles with corresponding verification via CSRD 3 This cycle is invalid when using CSRD for verification during data write erase operations 4 CEx is defined as the latter of CE0 or CE1 going low or the first of CE0 or CE1 going high 5 RP low transition is only to show tRHPL not valid for above Read and Write cycles 6 VPP voltage during write erase operations valid at both 12 0V and 5 0V 7 VPP voltage equal to or below VPPLK provides complete flash memory array protection Figure 14 AC Waveforms for Command Write Operations 39 VS28F016SV MS28F016SV FlashFile TM Memory 5 9 AC Characteristics for CE Versions Sym tAVAV tPHWL tVPEH (1 2) Controlled Command Write Operations(1) Unit ns ns ns ns ns ns ns ns ns ns ns ns 100 0 480 95 3 3 4 5 11 4 0 5 03 10 ns ns ns ns ms ms sec VCC e 3 3V g0 15V TCSE2 e b 40 C to a 125 C TCSE1 e b 55 C to a 125 C Load e 50 pF Parameter Write Cycle Time RP Setup to WE Going Low Going High Going Low Going High 3 37 37 267 267 7 High High 27 27 3 7 3 37 3 37 Notes Min 120 480 100 0 75 75 75 10 10 10 45 0 Max VPP Setup to CE WE Setup to CE tWLEL tAVEH tDVEH tELEH tEHDX tEHAX tEHWH tEHEL tGHEL tEHRL tRHPL tPHEL tEHGL tQVVL(1 2) tEHQV(1) tEHQV(2) Address Setup to CE Data Setup to CE CE Pulse Width Going High Data Hold from CE Address Hold from CE WE CE hold from CE High Pulse Width High Read Recovery before Write CE High to RY BY Going Low RP Hold from Valid Status Register (CSR GSR BSR) Data and RY BY High RP High Recovery to CE Going Low Write Recovery before Read VPP Hold from Valid Status Register (CSR GSR BSR) Data and RY BY High Duration of Word Byte Write Operation Duration of Block Erase Operation 40 VS28F016SV MS28F016SV FlashFile TM Memory 5 9 AC Characteristics for CE Controlled Command Write Operations(1) (Continued) VCC e 5 0V g0 25V TCSE2 e b 40 C to a 125 C TCSE1 e b 55 C to a 125 C Load e 30 pF VCC e 5 0V g0 5V TCSE2 e b 40 C to a 125 C TCSE1 e b 55 C to a 125 C Load e 100 pF Versions(4) Sym tAVAV tPHWL Parameter Write Cycle Time RP Setup to WE Going Low VPP Setup to CE Going High WE Setup to CE Going Low Address Setup to CE Going High Data Setup to CE Going High CE Pulse Width Data Hold from CE High Address Hold from CE High WE Hold from CE High CE Pulse Width High Read Recovery before Write CE High to RY BY Going Low RP Hold from Valid Status Register (CSR GSR BSR) Data and RY BY High 3 Notes VS MS28F016SV-85 VCC g5% Min 80 480 Max VS MS28F016SV-85 VCC g10% Min 85 480 Max VS MS28F016SV-100 VCC g10% Min 100 480 Max ns ns Unit tVPEH(1 2) 37 100 100 100 ns tWLEL 37 0 0 0 ns tAVEH 267 50 50 50 ns tDVEH 267 50 50 50 ns tELEH tEHDX tEHAX tEHWH tEHEL tGHEL tEHRL 7 27 27 37 7 3 37 50 10 10 10 30 0 100 60 10 10 10 30 0 100 70 10 10 10 30 0 100 ns ns ns ns ns ns ns tRHPL 3 0 0 0 ns 41 VS28F016SV MS28F016SV FlashFile TM Memory 5 9 AC Characteristics for CE VCC e 5 0V g0 25V TCSE2 e b 40 C to a 125 C TCSE1 e b 55 C to a 125 C Load e 30 pF VCC e 5 0V g0 5V TCSE2 e b 40 C to a 125 C TCSE1 e b 55 C to a 125 C Load e 100 pF (Continued) Versions(4) Sym tPHEL Parameter RP High Recovery to CE Going Low Write Recovery before Read VPP Hold from Valid Status Register (CSR GSR BSR) Data at RY BY High Duration of Word Byte Write Operation Duration of Block Erase Operation 3 Notes 37 VS MS28F016SV-85 VCC g5% Min 1 Max VS MS28F016SV-85 VCC g10% Min 1 Max Controlled Command Write Operations(1) VS MS28F016SV-100 VCC g10% Min 1 Max ms Unit tEHGL 60 65 70 ns tQVVL(1 2) 0 0 0 ms tEHQV(1) 3 4 5 11 45 45 45 ms tEHQV(2) 34 03 10 03 10 03 10 sec NOTES 1 Read timings during write and erase are the same as for normal read 2 Refer to command definition tables for valid address and data values 3 Sampled not 100% tested Guaranteed by design 4 Write erase durations are measured to valid Status Data VPP e 12 0V g 0 6V 5 Word Byte Write operations are typically performed with 1 Programming Pulse 6 Address and Data are latched on the rising edge of CE for all command write operations 7 CEx is defined as the latter of CE0 or CE1 going low or the first of CE0 or CE1 going high 8 Device speeds are defined as 80 85 100 ns at VCC e 5 0V equivalent to 120 ns at VCC e 3 3V 9 See the high speed AC Input Output Reference Waveforms and AC Testing Load Circuit 10 See the standard AC Input Output Reference Waveforms and AC Testing Load Circuit 11 The TBD information will be available in a technical paper Please contact Intel's Application Hotline or your local sales office for more information 42 VS28F016SV MS28F016SV FlashFile TM Memory 271312 - 24 NOTES 1 This address string depicts data-write erase cycles with corresponding verification via ESRD 2 This address string depicts data-write erase cycles with corresponding verification via CSRD 3 This cycle is invalid when using CSRD for verification during data write erase operations 4 CEx is defined as the latter of CE0 or CE1 going low or the first of CE0 or CE1 going high 5 RP low transition is only to show tRHPL not valid for above Read and Write cycles 6 VPP voltage during Write Erase operations valid at both 12 0V and 5 0V 7 VPP voltage equal to or below VPPLK provides complete flash memory array protection Figure 15 Alternate AC Waveforms for Command Write Operations 43 VS28F016SV MS28F016SV FlashFile TM Memory 5 10 AC Characteristics for WE Versions Sym tAVWL Parameter Address Setup to WE Controlled Page Buffer Write Operations(1) 28F016SV-120 Notes Min 25 Typ Max Unit ns VCC e 3 3V g0 3V TCSE2 e b 40 C to a 125 C TCSE1 e b 55 C to a 125 C Load e 50 pF Going Low 2 VCC e 5 0V g0 5V TCSE2 e b 40 C to a 125 C TCSE1 e b 55 C to a 125 C Load e 50 pF Versions(3) Sym tAVWL Parameter Address Setup to WE Going Low VCC g5% VCC g10% Notes 2 28F016SV-080(4) 28F016SV-080(5) Min 15 Typ Max 28F016SV-085(5) Min 15 Typ Max ns Unit NOTES Controlled Write Operations can be found in section 5 8 1 All other specifications for WE 2 Address must be valid during the entire WE low pulse 3 Device speeds are defined as 80 85 100 ns at VCC e 5 0V equivalent to 120 ns at VCC e 3 3V 4 See the high speed AC Input Output Reference Waveforms and AC Testing Load Circuit 5 See the standard AC Input Output Reference Waveforms and AC Testing Load Circuit 44 VS28F016SV MS28F016SV FlashFile TM Memory 271312 - 25 NOTE 1 CEX is defined as the latter of CE0 or CE1 going low or the first of CE0 or CE1 going high Figure 16 WE Controlled Page Buffer Write Timing Waveforms (Loading Data to the Tape Buffer) 45 VS28F016SV MS28F016SV FlashFile TM Memory 5 11 AC Characteristics for CE Versions Sym tAVEL Parameter Address Setup to CE Controlled Page Buffer Write Operations(1) 28F016SV-120 Notes Min 25 Typ Max Unit ns VCC e 3 3V g0 3V TCSE2 e b 40 C to a 125 C TCSE1 e b 55 C to a 125 C Load e 50 pF Going Low 23 VCC e 5 0V g0 5V TCSE2 e b 40 C to a 125 C TCSE1 e b 55 C to a 125 C Load e 50 pF Versions(4) Sym tAVEL Parameter Address Setup to CE Going Low VCC g5% VCC g10% Notes 23 28F016SV-080(5) 28F016SV-080(6) Min 15 Typ Max 28F016SV-085(6) Min 15 Typ Max ns Unit NOTES Controlled Write Operations can be found in section 5 9 1 All other specifications for CE 2 Address must be valid during the entire CE low pulse 3 CEx is defined as the latter of CE0 or CE1 going low or the first of CE0 or CE1 going high 4 Device speeds are defined as 80 85 100 ns at VCC e 5 0V equivalent to 120 ns at VCC e 3 3V 5 See the high speed AC Input Output Reference Waveforms and AC Testing Load Circuit 6 See the standard AC Input Output Reference Waveforms and AC Testing Load Circuit 271312 - 26 NOTE 1 CEx is defined as the latter of CE0 or CE1 going low or the first of CE0 or CE1 going high Figure 17 Controller Page Buffer Write Timing Waveforms (Loading Data to the Page Buffer) 46 VS28F016SV MS28F016SV FlashFile TM Memory 5 12 Erase and Word Byte Write Performance(3 5) VCC e 3 3V g0 15V VPP e 5 0V g0 5V TCSE2 e b 40 C to a 125 C TCSE1 e b 55 C to a 125 C Sym Parameter Page Buffer Byte Write Time Page Buffer Word Write Time tWHRH1A tWHRH1B tWHRH(2) tWHRH(3) Byte Write Time Word Write Time Block Write Time Block Write Time Block Erase Time Full Chip Erase Time Erase Suspend Latency Time to Read Auto Erase Suspend Latency Time to Write Notes 267 267 27 27 27 27 27 27 4 Typ(1) 8 16 29 35 19 12 14 44 8 12 15 Units ms ms ms ms sec sec sec sec ms ms Byte Write Mode Word Write Mode Test Conditions VCC e 3 3V g0 15V VPP e 12 0V g0 6V TCSE2 e b 40 C to a 125 C TCSE1 e b 55 C to a 125 C Sym Parameter Page Buffer Byte Write Time Page Buffer Word Write Time tWHRH(1) tWHRH(2) tWHRH(3) Word Byte Write Time Block Write Time Block Write Time Block Erase Time Full Chip Erase Time Erase Suspend Latency Time to Read Auto Erase Suspend Latency Time to Write Notes 267 267 27 27 27 2 27 4 Typ(1) 22 44 9 06 03 08 25 6 9 12 Units ms ms ms sec sec sec sec ms ms Byte Write Mode Word Write Mode Test Conditions 47 VS28F016SV MS28F016SV FlashFile TM Memory 5 12 Erase and Word Byte Write Performance(3 5) Sym Parameter Page Buffer Byte Write Time Page Buffer Word Write Time tWHRH1A tWHRH1B tWHRH(2) tWHRH(3) Byte Write Time Word Write Time Block Write Time Block Write Time Block Erase Time Full Chip Erase Time Erase Suspend Latency Time to Read Auto Erase Suspend Latency Time to Write Notes 267 267 27 27 27 27 27 27 4 (Continued) VCC e 5 0V VPP e 5 0V g0 5V TCSE2 e b 40 C to a 125 C TCSE1 e b 55 C to a 125 C Typ(1) 8 16 20 25 14 0 85 10 32 0 9 12 Units ms ms ms ms sec sec sec sec ms ms Byte Write Mode Word Write Mode Test Conditions VCC e 5 0V g 0 5V VPP e 12 0V g0 6V TCSE2 e b 40 C to a 125 C TCSE1 e b 55 C to a 125 C Sym Parameter Page Buffer Byte Write Time Page Buffer Word Write Time tWHRH(1) tWHRH(2) tWHRH(3) Word Byte Write Time Block Write Time Block Write Time Block Erase Time Full Chip Erase Time Erase Suspend Latency Time to Read Auto Erase Suspend Latency Time to Write Notes 267 267 27 27 27 2 27 4 Typ(1) 21 41 6 04 02 06 19 2 7 10 Units ms ms ms sec sec sec sec ms ms Byte Write Mode Word Write Mode Test Conditions NOTES 1 25 C and normal voltages 2 Excludes system-level overhead 3 These performance numbers are valid for all speed versions 4 Specification applies to interrupt latency for single block erase Suspend latency for erase all unlocked blocks operation extends the maximum latency time to 270 ms 5 Sampled but not 100% tested Guaranteed by design 6 Assumes using the full Page Buffer to Write to Flash (256 bytes or 128 words) 48 VS28F016SV MS28F016SV FlashFile TM Memory 60 MECHANICAL SPECIFICATIONS 271312 - 27 Figure 18 Mechanical Specifications of the VS MS28F0165V 56-Lead SSOP Package Family Shrink Small Out-Line Package Symbol A A1 A2 B C D E e1 He N L1 Y a b R1 R2 2 3 0 45 0 15 3 4 0 20 0 20 0 45 15 70 0 47 1 18 0 25 0 13 23 40 13 10 Millimeters Minimum Nominal 1 80 0 52 1 28 0 30 0 15 23 70 13 30 0 80 16 00 56 0 50 0 55 0 10 4 5 0 25 0 25 49 16 30 Maximum 1 90 0 57 1 38 0 40 0 20 24 00 13 50 Notes VS28F016SV MS28F016SV FlashFile TM Memory DEVICE NOMENCLATURE V M V e SE2 M e SE1 S S 2 2 8 8 F F 0 0 1 1 6 6 S S V V 8 8 5 5 l S e SSOP l Access Speed l SV e SmartVoltage Technology l l Depending on system design specifcations the VS MS28F016SV-85 is capable of supporting 85 ns access time with a VCC of 5 0V g10% and loading of 100 pF 100 ns access time with a VCC of 5 0V g10% and loading of 100 pF ADDITIONAL INFORMATION Order Number 297372 292163 292144 292127 292126 292124 292123 292092 292165 294016 297508 Contact Intel Distribution Sales Office Contact Intel Distribution Sales Office Contact Intel Distribution Sales Office Contact Intel Distribution Sales Office Contact Intel Distribution Sales Office Document Tool 16-Mbit Flash Product Family User's Manual AP-610 ``Flash Memory In-System Code and Data Update Techinques'' AP-393 ``28F016SV Compatibility with 28F016SA'' AP-378 ``System Optimization Using the Enhanced Features of the 28F016SA'' AP-377 ``16-Mbit Flash Product Family Software Drivers 28F016SA 28F016SV 28F016XS 28F016XD'' AP-387 ``Upgrade Considerations from the 28F008SA to the 28F016SA'' AP-374 ``Flash Memory Write Protection Techniques'' AP-357 ``Power Supply Solutions for Flash Memory'' AB-62 ``Compiling Optimized Code for Embedded Flash RAM Memories'' ER-33 ``ETOX TM Flash Memory Technology Insight to Intel's Fourth Generation Process Innovation'' FLASHBuilder Utility Flash Cycling Utility 28F016SV iBIS Models 28F016SV VHDL Verilog Models 28F016SV Timing Designer Library Files 28F016SV Orcad and ViewLogic Schematic Symbols DATA SHEET REVISION HISTORY Number 001 Description Original Version INTEL CORPORATION 2200 Mission College Blvd Santa Clara CA 95052 Tel (408) 765-8080 Printed in U S A xxxx 1295 B10M xx xx |
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